Stacked-chip-scale-package-design guidelines

You can configure the die stack for S-CSPs (stacked-die chip-scale packages) in multiple ways. However, using design guidelines can help you use die stacking for laminate-based and wire-bonded S-CSPs with more than 200 I/O pins. These packages typically find use in handheld products. When stacking mixed-technology dice, such as ASICs and memory, the challenge is often how to deal with wire-bond density. Wire-bond design must maximize the space between adjacent wires and minimize wire sweep—that is, wire misalignment in the horizontal plane. Wire sweep is undesirable because it can affect the inductance of adjacent wires, create noise, or cause a short when wires touch. Wiresweep problems can occur at various stages during the wire-bonding process.